As semiconductor technology has advanced into the deep submicron regime, the power supply, voltage is scaled down in concert with the scaling down of transistor dimensions. For example, microprocessors are now manufactured with transistors powered by a sub-one volt power supply voltage. But these modern systems may need to interface with peripheral devices such as memories that operate on higher supply voltages. The signal flow from the low-voltage domain to the high-voltage domain requires a shift up in voltage. Conversely, the signal flow from the high-voltage domain to the low-voltage domain requires a shift down in voltage. A conventional level-shifter 100 is shown in FIG. 1 that may perform such voltage level shifts between an input signal (IN) and an output signal (OUT). In this embodiment, the input signal is a low-voltage-domain (VDDL) signal whereas the output signal is a high-voltage-domain (VDDH) signal. However, level-shifter 100 is readily modified to instead shift down in voltage.
The input signal drives a gate of an NMOS transistor MN1. If the input signal is low (ground or VSS), transistor MN1 switches off, allowing a node N1 to float. The input signal also drives an inverter INV that produces an inverted input signal that in turn drives a gate of an NMOS transistor MN2. Inverter INV is powered by a power supply node providing the low-voltage-domain power supply voltage VDDL. Thus, inverter INV will charge the gate of transistor MN2 to VDDL when the input signal is low, which switches on transistor MN2 to pull node N2 to ground.
Node N2 couples to a gate of a PMOS transistor MP1 that has its drain coupled to node N1. Transistor MP1 is cross-coupled with a PMOS transistor MP2. The input signal also drives a gate of a PMOS transistor MP3 in series with transistor MP1. When the input signal is low, both transistors MP3 and MP1 will be on, which charges node N1 to a high-voltage-domain power supply voltage VDDH. Node N1 drives the gate of transistor MP2 coupled to node N2. Transistor MP2 will thus be off when the input signal is low. Another PMOS transistor MP4 that has its gate driven by the inverted input signal is in series with transistor MP3.
In response to the input signal switching high to VDDL, transistor MN1 will switch on and transistor MN2 will switch off. Output node N2, which had been discharged while the input signal was low, must then float until transistor MP2 can be switched on. In turn, transistor MP2 can't switch on until transistor MN1 can discharge node N1. However, transistor MP1 is still momentarily on and attempting to keep node N1 charged, which thus fights with transistor MN1 discharging node N1. Transistor MP3 is only weakly on because VDDL is effectively a weak zero with regard to VDDH. Transistor MP3 thus assists transistor MN1 in terms of discharging node N1 by restricting the flow of charge to transistor MP1. Once node N1 is discharged, transistor MP2 will switch on. Since transistor MP4 will already be on due to the inverted input signal being driven low, the switching on of transistor MP2 will charge the output signal to VDDH. An analogous struggle occurs between transistors MN2 and MP2 when the inverted signal is driven to VDDL in response to the input signal transitioning low.
This fight between the NMOS and PMOS transistors in level-shifter 100 may be alleviated by weakening PMOS transistors MP3 and MP1 (as well as transistors MP4 and MP2). But such a weakening adversely affects timing as each PMOS stack MP3/MP1 and MP4/MP2 must also pull up its corresponding node (N1 or N2, respectively) depending upon whether the input signal is high or low. There is thus a minimum amount of strength necessary for the PMOS stacks to meet desired timing requirements. Since the PMOS stacks must be left relatively strong, there is a limit to the voltage range for level-shifter 100. In that regard, as VDDL drops ever lower at the modern process nodes, transistor MP3 turns on ever stronger with regard to VDDL functioning as an effective zero in keeping transistor MP3 on despite the input signal transitioning high to VDDL. This input range for level-shifter 100 is also affected by the process corner. Should level-shifter 100 be manufactured in a process corner that makes NMOS transistors relatively weak compared to the corresponding PMOS transistors, the PMOS/NMOS struggle with regard to discharging node N1 is aggravated.
Accordingly, there is a need in the art for level-shifters with improved input voltage range and operating speed.